What will you do:
- Download Verilog code from GitHub, bring it up on a simulator, and successfully run tests.
- Make minor modifications to the code by removing features.
- Optimize the pipeline by adding a stage to increase performance.
- Optimize components such as barrel shifter and ALU.
- Work under direction from senior engineers and team leads.
- Collaborate with team members on design and implementation decisions.
- Completed Maths, Physics, or Applied Computer Science degree.
- Proven experience with Verilog and C++.
- Proven experience with FPGA development and their libraries and development tools.
- Good understanding of usual microprocessor core 5-stage pipeline, including hazards and how to address them.
- You have a strong development system with a simulator up and running with a high-power running computer.
- Strong desire to learn and develop in coding - you get carried away when you learn more about this topic.
- Analytical skills
Not necessary but will be a big plus:
- Experience with implementing multicore devices.
- Experience with implementing the simplest RISC-V 32I core.
- Experience with network on chip.
Your schedule can be flexible, but you should be ready to have 4 overlapping hours with the team between 10 am and 2 pm New York time, EST. (you may check the time difference via the link).
What we offer:
- Part-time schedule (4 working hours per day, 5/2).
- Remote work.